15.1 Processors, Parallel Processing and Virtual Machines

#### Type of Processor
##### Reduced Instruction Set Computers (RISC)
- Uses simple instructions
- Uses fixed length instructions
- Instructions only require one clock cycle
- Uses many registers
- Makes use of pipelining
- Hardwired CU

##### Complex Instruction Set Computers (CISC)
- Uses many instruction formats
- Uses variable length instructions
- Makes use of different addressing modes
- Uses few registers
- Has a large instruction set
- Requires complex circuits
- Frequently uses cache
- Instructions (converted to sub-instructions that) may require many clock cycles
- Programmable CU

| RISC                                                         | CISC                                           |
| ------------------------------------------------------------ | ---------------------------------------------- |
| RISC has fewer instructions                                  | CISC has more instructions                     |
| RISC has many registers                                      | CISC has few registers                         |
| RISC's instructions are simpler                              | CISC's instructions are more complex           |
| RISC has a few instruction formats                           | CISC has many instruction formats              |
| RISC usually uses single-cycle instructions                  | CISC uses multi-cycle instructions             |
| RISC uses fixed-length instructions                          | CISC uses variable-length instructions         |
| RISC has better pipelineability                              | CISC has poorer pipelineability                |
| RISC requires less complex circuits                          | CISC requires more complex circuits            |
| RISC has fewer addressing modes                              | CISC has more addressing modes                 |
| RISC makes more use of RAM                                   | CISC makes more use of cache/less use of RAM   |
| RISC has a hard-wired control unit                           | CISC has a programmable control unit           |
| RISC only uses load and store instructions to address memory | CISC has many types of instructions to address |

##### the use of pipelining in Reduced Instruction Set Computers (RISC)

- Pipelining allows several instructions to be processed simultaneously /concurrently.

- .. therefore, increasing the CPU instruction throughput / the number of instructions completed per unit of time.

- Each instruction stage / subtask is completed during one clock cycle
- No two instructions can execute their same stage of instruction / subtask at the same clock cycle.
- .. e.g., while one instruction is being decoded, the next instruction can be fetched, etc.

##### the process of pipelining during the fetch-execute cycle in RISC processors

- Instructions are divided into subtasks / 5 stages
- ... Instruction fetch / IF, Instruction decode / ID, operand fetch / OF, opcode/instruction execute IE, result store / write back result / WB
- Each subtask is completed during one clock cycle
- No two instructions can execute their same stage at the same clock cycle
- The second instruction begins in the second clock cycle, while the first instruction has moved on to its second subtask. 
- The third instruction begins in the third clock cycle while the first and second instructions move on to their second and third subtasks, respectively, etc.

|     | 1   | 2   | 3   | 4   | 5   | 6   | 7   | 8   | 9   | 10  | 11  | 12  |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| IF  | 1.1 | 2.1 | 3.1 | 4.1 | 5.1 | 6.1 |     |     |     |     |     |     |
| ID  |     | 1.2 | 2.2 | 3.2 | 4.2 | 5.2 | 6.2 |     |     |     |     |     |
| OF  |     |     | 1.3 | 2.3 | 3.3 | 4.3 | 5.3 | 6.3 |     |     |     |     |
| IE  |     |     |     | 1.4 | 2.4 | 3.4 | 4.4 | 5.4 | 6.4 |     |     |     |
| WB  |     |     |     |     | 1.5 | 2.5 | 3.5 | 4.5 | 5.5 | 6.5 |     |     |

##### characteristics of massively parallel computers
- A large number of computer processors / separate computers connected together
- ... simultaneously performing a set of coordinated computations collaborative processing
- network infrastructure
- communicate using a message interface / by sending messages.
##### Four categories of computer architecture  used in parallel processing

###### Single Instruction Single Data (SISD)
single instruction single data, computer architecture which uses a single processor and one data source.
###### SIMD
many/array processors execute the same instruction using different data sets
###### MISD
many processors (using different instructions) use the same data set
###### MIMD
many processors (using different instructions) using different data set

##### virtual machine

- The emulation of a computer system / hardware and/or software
- ...using a host computer system.
- Using guest operating system(s) for emulation.

###### Benifits

- New system can be tried on different virtual hardware
- without need to purchase the hardware

- Easier to recover if software emulating the new computer causes system crash
- as VM provides protection to other software

- Emulate programs for the new computer system that are not compatible with the host computer / operating system
- by using the guest operating system on the old computer

- More than one new computer system can be emulated
- this allows multiple operating systems to coexist on a single computer

- There are security benefits // Trying a piece of suspicious software and if it is / has a virus, it will only infect the virtual machine.

###### limitation

- Virtual machines may not be able to emulate the new hardware
- because this hardware may have been developed since the virtual machine was developed

- Using virtual machine means execution of extra code // A virtual machine might not be as efficient // resources e.g. memory or processor time are shared
- processing time increased // performance degrades

- Use of a virtual machine increases the maintenance overheads
- because both host system and the virtual machine must be maintained